Compilation and Pipeline Synthesis for Reconfigurable Architectures

This paper gives a survey of a novel programming method for reconfigurable architectures. It combines techniques from vectorizing compilers, high-level synthesis, and hardware/software codesign: An imperative high-level language program specifies both the host program (software) and the coprocessor configuration (hardware) of the application. This renders reconfigurable architectures useful for users without hardware design experience. First, the input program is analyzed and vectorized. Then, for suitable loops, hardware pipelines are synthesized. They execute the loops’ operators in parallel on the reconfigurable hardware, thus speeding up the program. Finally, a partitioner dynamically selects software or hardware execution for every loop. To show the feasibility of this method, we have built a prototypical “pipeline compiler”. It automatically synthesizes coprocessors and integrates their configuration and control within the host program. Results of some experiments on a small FPGA board using this compiler are presented.